The FFT Card consists of the following sections:
1.The Input Section and the Fringe Rotator:
The 4-bit wide ECL data input gfrom the delay sub-system is converted to TTL levels by a MC10125, latched using a 74F574 and fed to the fringe rotator. The fringe rotator is implemented as a lookup table with the data and the NCO as its inputs. The NCO initial phase and rate of increment ids programmed appropriately to compensate for the fringe modulation. The lookup table is implemented by two synchronous ROMs ( CY7C265 ), one of which handles the sign bits of both the real and imaginary parts apart from real part while the other handles the imaginary and exponent bits. The output of the fringe rotator is in the form ( 7,7,2 ) with the other two exponent bits are permanently wired to ground aat the input of the ASIC.
2.The FFT Pipe-line:
The fringe rotator output forms the input to the FFT pipe-line. The pipe-line comprises of 5 FX ASICs, each of them operating in FFT mode-either Radix-4 or Radix-2 or Radix-4 bypass. The 5 ASIC are configured as sstage 0,1,2,3 and 5 respectively. Stage 0, in addition, also accepts a window function in ( 5,0,4 ) format as
its twiddle input. All othre stages, from stage 1 to stage 3, operate on internal addresses and external twiddle factors. The output of one forms the input of next.
3.The Output Section:
The Output Section comprises of the outputs from the two pipelines into a single output. This is done to conserve the output lines coming out from the FFT card. Advantage is taken of the fact that the spectrum of real data will be Hermitian symmetric, only half of it need be read out of the chip. Thus, the output can be either the positive half or the negative half. Since the output noe will contain only half as many numbers as the input, the readout frequency is also half that of the processing frequency. And, since the output transmission is capable of handling 32MHz data, the two 16MHz output of the pipeline process data from two polarisations of the same-band. There are time-multiplexed in the output. Such a time multiplexing is also necessary for operating the MAC in the polar mode.
4.On-Board RAMs and other circuitry:
The rest of tghe logic of the FFT card includes the clock distribution circuitry ( clock driver-74ACT11208 ), controll circuitry for loading the on-board RAMs ( latches-74F574 ), and capturing circuitry for the trigonometric tables/synchronising signals ( latches-74F821 and 75F574 ). The RAMs ( CY7C199 and CY7C128A ) contain external addresses for the first and last stage FFT and a few synchronising signals. These RAMs are loaded under microprocessor control by the FFT control card during the start of each session.